Tbf, I am not a grey beard chief engineer, and I strongly prefer VHDL for design. For verification I actually really like SystemVerilog.

VHDL is strongly types, which prevents a lot of issues with types that I’ve hit with [System]Verilog.

Also, having learned VHDL first, I think it is easier to go from VHDL to Verilog, as opposed to vice versa. And this is mainly because VHDL is stricter.

Lol, so much of the FPGA industry 🤣. Especially East coast of the US

Same here.

VHDL represent. Although it’s arguably not a “programming language”

Off topic: how do you like simplex. I have heard of it, but you’re the first I’ve encountered who used it.