I wanted to learn hardware design by designing a basic risc-v processor, ben eater style, kind of like a 1970s minicomputer, with expansion slots for new isa extensions and CSRs. But obviously using real breadboards for experimentation would be too slow when designing a 32 bit processor. I had never touched an hdl before.

So I sat down and started writing my own simulator and netlist generation dsl from scratch. It only works at the gate level, no behavioral synthesis, but flexible enough to write components modelling, for example, 74 series chips. It does vhdl-like delta cycle simulation using 8-valued logic, but without vhdl’s signal forwarding footgun.

I then implemented an rv32i processor with full m-mode support, and a risc-v emulator in rom to trap and silently emulate any missing extension instructions. When a new expansion board is plugged in, those instructions are simply not trapped and are accelerated in hardware.

I then learned just enough systemverilog to faithfully transliterate the generated netlist into structural verilog, and it actually synthesized and worked perfectly on an fpga.

I am now in the process of very slowly designing boards to hopefully one day manage to build the whole thing out of discrete 74hc series logic